Recently, the WL-CSP (Wafer Level-Chip Size Package, hereinafter referred to simply as “WL-CSP”) technology has been increasingly employed in practical applications for higher performance and multifunctional semiconductor devices. With the WL-CSP technology, a packaging step is completed at the wafer level, and a chip size obtained by dicing is equal to a package size.
As shown in FIG. 19, a semiconductor device based on the WL-CSP technology includes a semiconductor chip 82 having a surface covered with a surface protective film 81, a stress relief layer 83 provided on the surface protective film 81 and a metal ball (e.g., solder ball) 84 provided on the stress relief layer 83. The surface protective film 81 has a pad opening 86 from which a part of an internal interconnection of the semiconductor chip 82 serving as an electrode pad 85 is exposed. The stress relief layer 83 has a through-hole 87 through which the electrode pad 85 exposed from the pad opening 86 is exposed.
A bump underlying layer 88 of a metal such as titanium covers a surface of the electrode pad 85, an interior surface of the through-hole 87 and a surface portion of the stress relief layer 83 around the through-hole 87. The metal ball 84 is provided on the bump underlying layer 88, and electrically connected to the electrode pad 85 via the bump underlying layer 88. The semiconductor device is mounted on a mount board 89 (or is electrically and mechanically connected to the mount board) by connecting the metal ball 84 to a pad 90 on the mount board 89.
Patent Document 1: JP-A-8(1996)-340002